The present invention relates to a semiconductor integrated circuit device. In particular, the present invention relates to a technique effectively applied to a system LSI for a portable device or a microprocessor.
In recent years, with high integration caused by a finer semiconductor manufacturing process, an SoC (System-on-a-Chip) has been generally known. As such, systems integrated on an LSI are known. However, with this finer process, a leakage current in each transistor has increased more and more, and a leakage current of the whole SoC chip has become very large. Conventionally, this leakage current has been thought to be important in a so-called standby state. However, this leakage current is becoming a problem at the time of operation.
For example, in the SoC for a portable cellular phone, the circuit scale has become tremendously large. In the future, it is expected that, in the worst state, about 1/10 of an operating current will be occupied by a leakage current. The SoC applied to a portable cellular phone is presumed as being driven by batteries. Moreover, because of its small size, its battery capacitance is limited. Thus, even at the time of operation, it is important to reduce this leakage current in order to have long time operation of a cellular phone device. A technique of using a circuit operated at different power supplies as a relay buffer (patent document 1) is known as a conventional technique.
In order to reduce a leakage current of the SoC, there is proposed a technique of subdividing a power domain inside of the chip, and then, selectively shutting down the power supply (patent document 2 and non-patent document 1)
[Patent document 1] Japanese Patent Laid-open Publication No. 2003-78009
[Patent document 2] Japanese Patent Laid-open Publication No. 2003-218682
[Non-patent document 1] ‘μI/O Architecture for 0.13-μm Wide-Voltage-Range System-on-Package (SoP) Design’ 2002 Symposium on VLSI circuits Digest of Technical Papers, pp. 168 to 169, June, 2002